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حل اسئلة معمارية قسم الحاسوب الجامعة المستنصرية نموذج رقم 1

 حل اسئلة معمارية قسم الحاسوب الجامعة المستنصرية نموذج رقم 1
حل اسئلة معمارية قسم الحاسوب الجامعة المستنصرية نموذج رقم 1




Q1. Chose the correct answer [15 mark]

1) The small extremely fast, memory all called as ________

A. Cache B. Heaps C. Accumulator D. Stack

2) The processor's internal components are connected by ________

A. Processor intra- connectivity B. Processor Bus C. Memory bus D. RAMbus

3) Data is stored in registers via ________

A. D flip flop B. JK flip flop C. RS flip flop D. None of above

4) When we perform subtraction on -7 and -5 the answer in 2’s complement form is

A. 11110 B. 1110 C. 1010 D. 0010

5) If a system is 64 bit machine, then the length of each word will be

A. 4 bytes B. 8 bytes C. 16 bytes D. 12 bytes

6) The requested data resides in a given level of memory is _________

A. Hit B. Miss C. average memory access D. None of above

7) Which of the following memories must be refreshed many times per second?

A. EPROM B. ROM C. Static RAM D. Dynamic RAM

8) How many memory locations can be addressed by a CPU with 14 address lines?

A. 2K B. 4K C. 8K D. 16K

9) In relative address mode the effective address is --------

A. AC + Relative address

B. PC + Relative address

C. IR + Relative address

D. BR + Relative address

10) ----------operation performs bit manipulation on numeric data.

A. Register Transfer B. Arithmetic C. Logical D. Shift

11) How many possible outputs would a decoder have with a 6-bit binary input?

A. 16 B. 32 C. 64 D. 128

12) A combinational circuit that selects one from many inputs are----------

A. Encoder B. Decoder C. Demultiplexer D. Multiplexer

13) There are ----------- categories of the most common microoperations.

A. two B. three C. Four D. Five

14) The __________ moves data between the computer and its external environment.

A. data transport B. I/O C. CPU interconnection D. register

15) How many address and data lines will be there for a 16M x 32 memory system?

A. 24 and 5 B. 20 and 32 C. 24 and 32 D. None of the above


Q2) state whether TRUE or FALSE [10 mark]

1. Register is implemented inside the main memory on computer board. False

2. Static RAM is typically used to implement Cache . True

3. The main memory of a computer system provides random access. True

4. The main objective for using cache memory is to increase the effective speed of the

memory system. True

5. Control bus is a group of lines used for the purpose of data flow. True

6. 1011-1001-1001 = -0011. False

7. PROM can be erasable . False

8. The memory is the brain of the computer. False

9. A bus is a collection of wires that carry information as electrical signals between the

hardware components of a computer. True

10. A kilobyte of storage is 210 = 1,024 bytes, where a byte is a collection of eight bits. True



Q3) Answer Two questions only [20 mark]
A) Suppose you have an addition of 2 register, what is the HW implementation of
t: R1 ← R1+R2

Sol//

اقرأ محتويات R1 وR2:
تقوم وحدة التحكم بقراءة القيم المخزنة في المسجلين R1 وR2.
أضف القيم:
تقوم ALU (وحدة المنطق الحسابي) بتنفيذ عملية الجمع على القيم التي تم الحصول عليها من R1 وR2.
يتم تخزين نتيجة الإضافة في سجل مؤقت.
الكتابة مرة أخرى إلى R1:
وأخيرًا، تقوم وحدة التحكم بكتابة النتيجة مرة أخرى لتسجيل R1.

B) Assume, hit rate of 75 percent at a level of the memory hierarchy, memory requests take 12
ns to complete if they hit in the level, and memory requests that miss in the level take 100
ns to complete Find the Average access time.

Sol//

To find the average access time in this memory hierarchy, we need to consider both the hit time and the miss penalty, weighted by their respective probabilities.

Given:
- Hit rate (H) = 75% = 0.75
- Miss rate (M) = 1 - H = 1 - 0.75 = 0.25
- Hit time (T_hit) = 12 ns
- Miss penalty (T_miss) = 100 ns

Average Access Time (T_avg) = (H * T_hit) + (M * T_miss)

Substituting the given values:

T_avg = (0.75 * 12 ns) + (0.25 * 100 ns)

Calculating:

T_avg = (9 ns) + (25 ns)

T_avg = 34 ns

So, the average access time is 34 ns.

C) Let the decimal numbers A=54, B= -77 , Compute A-B in 2’s complement, is it overflow ?
why or why not ?
Sol//

Certainly! Let’s compute the subtraction of A and B using 2’s complement representation.

  1. Convert Decimal Numbers to Binary (2’s Complement):

    • A = 54:
      • The binary representation of 54 is 00110110.
    • B = -77:
      • To find the 2’s complement of -77, follow these steps:
        1. Represent 77 in binary: 01001101.
        2. Invert all the bits: 10110010.
        3. Add 1 to the inverted value: 10110011.
  2. Perform Subtraction:

    • We’ll subtract B from A:
      00110110 (A)
      
    • 10110011 (2’s complement of B)

      01100001
    • The result in binary is 01100001.
  3. Convert Binary Result to Decimal:

    • The binary result 01100001 represents a positive number.
    • Converting it to decimal: 2^6 + 2^5 + 2^0 = 64 + 32 + 1 = 97.
  4. Check for Overflow:

    • In 4-bit 2’s complement representation, we can represent numbers from -8 to 7.
    • The result (97) lies outside this range.
    • Therefore, there is an overflow.

In summary:

Q4) Answer Two questions only [20 mark]
A) Design 3-to-8 decoder? Write its truth table and draw its internal logic diagram?
Sol//

To design a 3-to-8 decoder, we need 3 input lines and 8 output lines. The truth table for a 3-to-8 decoder is as follows:

| A | B | C | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 |
|---|---|---|----|----|----|----|----|----|----|----|
| 0 | 0 | 0 |    1 |   0 |    0 |    0 |    0 |    0 |    0 |    0 |
| 0 | 0 | 1 |    0 |   1 |    0 |    0 |    0 |    0 |    0 |    0 |
| 0 | 1 | 0 |    0 |   0 |    1 |    0 |    0 |    0 |    0 |    0 |
| 0 | 1 | 1 |    0 |   0 |    0 |    1 |    0 |    0 |    0 |    0 |
| 1 | 0 | 0 |    0 |   0 |    0 |    0 |    1 |    0 |    0 |    0 |
| 1 | 0 | 1 |    0 |   0 |    0 |    0 |    0 |    1 |    0 |    0 |
| 1 | 1 | 0 |    0 |   0 |    0 |    0 |    0 |    0 |    1 |    0 |
| 1 | 1 | 1 |    0 |   0 |    0 |    0 |    0 |    0 |    0 |    1 |

In the truth table, each combination of inputs (A, B, C) corresponds to one of the eight output lines (Y0 to Y7). Each output line is active (logic 1) for only one combination of inputs.

The internal logic diagram of a 3-to-8 decoder typically consists of a set of AND gates connected to the input lines and their complements (if required), followed by OR gates to generate the output lines. Here's a simplified diagram:

```
        A
        |
        +---\           +--- Y0
        |   AND Gate ---|
        +---/           +--- Y1
        |
        +---\           +--- Y2
        |   AND Gate ---|
        +---/           +--- Y3
        |
        +---\           +--- Y4
        |   AND Gate ---|
        +---/           +--- Y5
        |
        +---\           +--- Y6
        |   AND Gate ---|
        +---/           +--- Y7
   B    |
        +---\
        |   AND Gate
        +---/
   C    |
        +---\
        |   AND Gate
        +---/
```

Each input line (A, B, C) is connected to a set of AND gates. The output of each AND gate is connected to one of the output lines (Y0 to Y7). The output lines are activated (set to logic 1) based on the combination of inputs specified in the truth table.

B) What is the Huffman code of the following set:
 
Symbol       A              B          C       D         E        F
Probability 0.074    0.366       0.1    0.22    0.06    0.18

Sol//

To find the Huffman code for the given set of symbols and their probabilities, we can follow these steps:

1. Arrange the symbols in ascending order based on their probabilities.
2. Create a binary tree where each leaf node represents a symbol and its probability, and the parent nodes represent combined probabilities.
3. Assign binary codes to the symbols by traversing the tree, assigning '0' to left branches and '1' to right branches.

Let's go through the process:

1. Arrange symbols in ascending order based on probabilities:
   ```
   Symbol    E    A    C    F    D    B
   Probability 0.06 0.074 0.1 0.18 0.22 0.366
   ```
2. Build the Huffman tree:
   Start with the two symbols with the lowest probabilities:
   ```
        [E, 0.06]     [A, 0.074]     [C, 0.1]     [F, 0.18]     [D, 0.22]     [B, 0.366]
             |               |                 |                 |                 |   
   ```
   Combine the two lowest probabilities to create a new parent node:
   ```
                  [E, 0.06]     [A, 0.074]     [C, 0.1]     [F, 0.18]     [D, 0.22] + [B, 0.366]
                        |               |                 |                 |              |
                                    [E, 0.06] + [A, 0.074]
   ```
   Continue this process until all nodes are connected.
3. Assign binary codes:
   - Traverse the tree, assigning '0' to left branches and '1' to right branches.
   - The binary codes for each symbol are:
     ```
     E: 00
     A: 01
     C: 100
     F: 101
     D: 110
     B: 111
     ```

So, the Huffman code for the given set of symbols and probabilities is:
```
Symbol    | Probability | Huffman Code
---------------------------------------
A             | 0.074               | 01
B             | 0.366               | 111
C             | 0.1                   | 100
D             | 0.22                 | 110
E             | 0.06                 | 00
F             | 0.18                 | 101
```


C) Use AND, OR, and NOT logic circuits to draw a combinational logic block that produces the sum output of a 1-bit adder. Label clearly inputs and the output.
Sol//

1-Bit Adder with AND, OR, and NOT Gates

Here's the combinational logic block for a 1-bit adder using AND, OR, and NOT gates:

Inputs:

  • A: One binary input bit
  • B: Another binary input bit

Output:

  • Sum: The sum bit of the addition (XOR of A and B)

Circuit Diagram:

      A
     / \
    /   \
   /     \
  /       \
 NOT(A)   B
  \       /
   \     /
    \   /
     \ /
      |
     XOR
      |
     / \
    /   \
   /     \
  Sum    Carry

Explanation:

  1. XOR Gate: The XOR gate takes A and B as inputs. Its output represents the Sum of the 1-bit addition. XOR produces a 1 when the inputs are different (0 and 1 or 1 and 0), resulting in a sum of 1 without a carry. When both inputs are the same (0 and 0 or 1 and 1), the XOR outputs a 0, indicating a sum of 0, but potentially with a carry (explained next).

  2. Implicit Carry: In this design, a separate carry output is not explicitly shown. However, you can understand the carry situation by analyzing the combination of inputs:

    • If A and B are both 1, the XOR will output 0 (sum = 0), but there's a carry-out since two 1s are being added. This carry would need to be propagated to the next higher bit position in a multi-bit adder.

Alternative Implementation (Explicit Carry):

Here's a variation of the circuit with an explicit Carry output using an additional AND gate:

      A
     / \
    /   \
   /     \
  /       \
 NOT(A)   B
  \       /
   \     /
    \   /
     \ /
      |
     AND
      | (A AND B)
     / \
    /   \
   /     \
  Sum    Carry
  • In this version, an AND gate takes A and B as inputs. It outputs a 1 only when both A and B are 1, indicating a carry situation (Carry = A AND B).
  • The Sum output remains the same (XOR of A and B).

Both implementations achieve the same functionality for a 1-bit adder. The choice depends on your specific needs and how you want to handle the carry signal in a larger multi-bit adder.


Practical Exam:

Write the assembly language program using (Conditional Jumps and
Unconditional jump instruction) to build a procedure that receives two variables
(Var1= 1, Var2= 2) in AL and BL registers, multiplies these variables and returns
the result in AX register.

For I = 1 to 100 do
Z = X * Y
Sol//





section .data
    Var1    db 1          ; Variable Var1 initialized with value 1
    Var2    db 2          ; Variable Var2 initialized with value 2

section .text
    global _start

_start:
    ; Load Var1 into AL and Var2 into BL
    mov al, [Var1]
    mov bl, [Var2]

    ; Initialize AX register to 0 (to store the result)
    xor ax, ax

    ; Loop counter initialization
    mov cx, 100

loop_start:
    ; Multiply AL and BL and store the result in AX
    mul bl

    ; Check if loop counter (CX) is equal to 1
    cmp cx, 1
    je loop_end     ; If CX = 1, jump to loop_end (to exit the loop)

    ; Decrement loop counter
    dec cx

    ; Jump to loop_start to continue the loop
    jmp loop_start

loop_end:
    ; Program ends here

    ; Exit the program
    mov eax, 1      ; syscall number for exit
    xor ebx, ebx    ; exit status 0
    int 0x80       ; invoke syscall
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